Data recording method and apparatus, data record medium and data reproducing method and apparatus

ABSTRACT

An input is ciphered in at least one of a sector forming circuit  13 , a scrambling circuit  14 , a header appendage circuit an error correction encoding circuit  16 , a modulation circuit and a synchronization appendage circuit  18 , used for processing input data for forming a recording signal. Not only key for ciphering itself in the circuits but also the information as to which of the circuits has been used for ciphering becomes the key for ciphering. This realizes ciphering difficult to decode by a simplified structure.

TECHNICAL FIELD

[0001] This invention relates to a data recording method and apparatus,a data record medium and a data reproducing method and apparatusapplicable to prevention of copying or inhibition of unauthorized useand to a charging system.

BACKGROUND ART

[0002] Recently, with increased capacity and coming into widespread useof a digital record (recording, recordable or recorded) medium,increasing importance is attached to prevention of copying or inhibitionof unauthorized use. That is, since digital audio data or digital videodata can be duplicated free of deterioration by copying or dubbing,while computer data an be easily copied to produce the same data as theoriginal data, unauthorized copying is made frequently.

[0003] For avoiding unauthorized copying of the digital audio or videodata, there is known a standard such as a so-called serial copyingmanagement system (SCMS) or copy generation management system (CGMS).Since these systems set a copying inhibition flag on a specified portionof record data, a problem is raised that data can be extracted by dumpcopying which is the copying of a digital bi-level signal in itsentirety.

[0004] It is also practiced to cipher the contents of a file itself incase of computer data and to permit use only by regular registered user,as disclosed in, for example, Japanese Patent laid-Open No.SHO-60-116030. This is connected to a system in which a digital recordmedium having the ciphered information recorded thereon is distributedas a form of information circulation and in which the user pays a feefor the information he or she needs to acquire a key to decipher theinformation for use. For this system, a simplified useful technique forciphering has been a desideratum.

[0005] In view of the above-depicted status of the art, it is an objectof the present invention to provide a data recording method andapparatus, a data record medium and a data reproducing method andapparatus whereby ciphering can be realized by a simplified structure,prevention of copying or unauthorized use can be achieved by asimplified configuration, deciphering is rendered difficult and relativefacility or depth of ciphering can be controlled easily.

DISCLOSURE OF THE INVENTION

[0006] The recording method according to the present invention ischaracterized in that an input is ciphered in at least one of a sectorforming step of dividing input digital data in terms of a pre-set datavolume as a unit, a header appendage step, an error correction anddecoding step, a modulation step for effecting modulation in accordancewith a pre-set modulation system, or a synchronization appendage stepfor appendage of a synchronization pattern. A scrambling step ofeffecting randomizing for eliminating the same pattern may be includedamong the steps that can be used for ciphering.

[0007] This data recording method can be applied to a data recordingapparatus.

[0008] A data reproducing method according to the present invention ischaracterized in that, in reproducing a data record medium recorded inthe above data recording method, an input has been ciphered in arecording step corresponding to at least one of a synchronizationseparation step, a demodulating step, an error correction and decodingstep, a sector resolving step and a header separation step, and in thatthe input is decoded in a reproducing step corresponding to therecording step used for ciphering. A descrambling step of descramblingfor scrambling used for recording may be included among the steps thatcan be used for deciphering.

[0009] The data reproducing method can be applied to a data reproducingapparatus.

[0010] With the data recording method according to the presentinvention, the above object is accomplished by ciphering the data usingthe pre-set key information and by using the information written in anarea different from a data recording area of the record medium as atleast a portion of the key information for ciphering. This can beapplied to the data recording apparatus and to a data record medium.

[0011] The data reproducing method according to the present invention isalso characterized in that, in reproducing the digital signal cipheredduring recording, deciphering is done using the key information at leastpart of which is the information written in an area different from adata recording area of the record medium.

[0012] This can be applied to a data reproducing apparatus.

[0013] The data recording method according to the present invention isalso characterized by varying at least one of the initial value of thescrambling step or the generating polynominal depending on the keyinformation for ciphering.

[0014] The data reproducing method according to the present invention isalso characterized by descrambling by varying at least one of theinitial value or the generating polynominal based upon the keyinformation used for recording.

[0015] The input digital data is divided into sectors in terms of apre-set data volume as a unit, and the resulting data is processed withheader appendage, error correction and encoding, modulation by a pre-setmodulation system and appendage of a synchronization pattern forrecording on a record medium. By ciphering an input in at least one ofthe above steps, the particular step in which ciphering has been domealso becomes a key for ciphering thus raising the difficulty indeciphering.

[0016] At least a portion of the key information for ciphering iswritten in an area different from the recording area on the recordmedium. This portion of the key information is read out at the time ofreproduction and used for deciphering. Since the key information is notcompleted with the information in the data recording area on the recordmedium, difficulty in deciphering is increased.

[0017] At least one of the generating polynominal or the initial valueis varied depending on the key for ciphering at the time of scramblingaimed at randomization for removing the same pattern in a data string.Any conventional scrambling may be used for ciphering.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic block diagram showing the configuration of afirst embodiment of a data recording apparatus of the present invention.

[0019]FIG. 2 is a block diagram showing an illustrative construction forrealizing interleaving of even and odd bytes in a sector formingcircuit.

[0020]FIG. 3 illustrates interleaving of even and odd bytes.

[0021]FIG. 4 illustrates an example of a scrambler.

[0022]FIG. 5 illustrates an example of pre-set values of the scrambler.

[0023]FIG. 6 illustrates an example of a scrambler having variablegenerating polynomials.

[0024]FIG. 7 illustrates an example of a sector format.

[0025]FIG. 8 illustrates an example of ciphering in a synchronizationarea in a sector.

[0026]FIG. 9 illustrates an example of a header area in a sector.

[0027]FIG. 10 illustrates a schematic structure of an error correctionencoding circuit.

[0028]FIG. 11 illustrates a specified structure of an error correctionencoding circuit.

[0029]FIG. 12 illustrates another example of an error correctionencoding circuit.

[0030]FIG. 13 illustrates an example of ciphering in a modulationcircuit.

[0031]FIG. 14 illustrates a specified example of a sync word appended toa modulated signal.

[0032]FIG. 15 illustrates an example of ciphering in a sync appendingcircuit.

[0033]FIG. 16 illustrates an example of a data record medium.

[0034]FIG. 17 is a block diagram showing a schematic structure of afirst embodiment of a data reproducing apparatus according to thepresent invention.

[0035]FIG. 18 illustrates an example of deciphering by a demodulationcircuit.

[0036]FIG. 19 illustrates a schematic structure of an example of anerror correction decoding circuit.

[0037]FIG. 20 illustrates a specified structure of an example of anerror correction decoding circuit.

[0038]FIG. 21 illustrates another example of an error correctiondecoding circuit.

[0039]FIG. 22 illustrates an example of a descrambling circuit.

[0040]FIG. 23 illustrates another example of a scrambler.

[0041]FIG. 24 illustrates an example of pre-set values of the scramblerof FIG. 23.

[0042]FIG. 25 illustrates an example of a header area in a sector in asector format of FIG. 25.

[0043]FIG. 26 illustrates an example of a header area in a sector in thesector format of FIG. 25.

[0044]FIG. 27 is a block diagram showing another example of an errorcorrection encoding circuit.

[0045]FIG. 28 illustrates a product code as a specified example of theerror correction code.

[0046]FIG. 29 illustrates an example of a sector signal format.

[0047]FIG. 30 illustrates another specified example of a sync wordappended to the modulated signal.

[0048]FIG. 31 illustrates another example of ciphering in a syncappendage circuit.

[0049]FIG. 32 is a block diagram showing another example of an errorcorrection decoding circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0050] Referring to the drawings, preferred embodiments of the presentinvention will be explained in detail.

[0051]FIG. 1 schematically shows a first embodiment of the presentinvention.

[0052] In FIG. 1, digital data, such as data obtained on digitalconversion of analog audio or video signals or computer data, are fed toan input terminal 11. The input digital data is sent via an interfacingcircuit 12 to a sector forming circuit 13 so as to be formed intosectors in terms of a pre-set data volume, such as 2048 bytes, as aunit. The data thus formed into sectors is sent to a scrambling circuit14 for scrambling. For scrambling, the input data is randomized so thatthe same byte pattern will not be produced in succession, that is sothat the same patterns will be eliminated, by way of randomizing, forenabling the signal to be read and recorded appropriately. The scrambledor randomized data is sent to a header appendage circuit 15 where headerdata to be arrayed at the leading end of each sector is appended and theresulting data is sent to an error correction encoding circuit 16. Theerror correction encoding circuit 16 delays the data and generatesparity to append the generated parity. The next circuit, that is amodulation circuit 17, converts the 8-bit data into 16 channel-bitmodulated data in accordance with a pre-set modulation rule and sendsthe resulting modulated data to a synchronization appendage circuit 18.The synchronization appendage circuit 28 appends a synchronizationsignal violating the modulation rule of the above pre-set modulationsystem, that is a so-called out-of-rule pattern synchronization signal,in terms of a pre-set data volume asa unit, and sends the resultingsynchronization signal via a driving circuit, that is a driver 19, to arecord head 20. The record head 20 performs optical or magneto-opticalrecording and records the modulated signal on the record medium. Thedisc-shaped record medium 21 is run in rotation by a spindle motor 22.

[0053] The scrambling circuit 14 is not essential. Moreover, thescrambling circuit 14 may be inserted downstream of the header appendagecircuit 15 for scrambling the digital data having the header appendedthereto. The digital data having the header appended thereto may be sentto the error correction encoding circuit 16.

[0054] It should be noted that at least one of the sector formingcircuit 13, scrambling circuit 14, header appendage circuit 15, errorcorrection encoding circuit 16, modulation circuit 17 and thesynchronization appendage circuit 18 is configured for ciphering aninput and outputting the resulting ciphered signal. Preferably, two ormore circuits are used for ciphering. The key information for thisciphering uses, as at least a portion thereof, the identificationinformation written in an area other than the data record area of therecord medium 21, such as the identification information proper to themedium, the producer identification information, dealer identificationinformation, the identification information proper to the recordapparatus or the encoder, the identification information proper to themedium producing apparatus, such as a cutting machine or a stamper, theterritory information, such as a country code or the identificationinformation furnished from outside. Such identification informationwritten in this manner in an area other than the data record area of therecord medium is the information sent from the interfacing circuit 12via a contents-contents (TOC) generating circuit 23 to a terminal 24,and is the information sent directly from the interfacing circuit 12 toa terminal 25. The identification information from these terminals 24,25 is used as a portion of the key information for ciphering. At leastone and preferably two or more of the circuits 13 to 18 performciphering on the input data using the key information. Theidentification information from these terminals 24, 25 is sent asappropriate to the record head 20 for recording on the record medium 21.

[0055] In this case, which of the circuits 13 to 18 has performedciphering represents one of the alternatives, and is felt to be a keynecessary for producing the regular reproduced signal on reproduction.That is, if ciphering has been performed in one of the circuits, itbecomes necessary to select one of six alternatives, whereas, ifciphering has been performed in two of the circuits, it becomesnecessary to select one of 15 alternatives corresponding to the numberof combinations of two out of six circuits. If there is the possibilityof the ciphering operation performed in one to six of the six circuits13 to 18, the number of alternatives is increased further, such that itbecomes difficult to find the combination by a trial-and-error method,thus fulfilling the role of ciphering.

[0056] The key information for ciphering may be switched at a pre-settiming, for example, on the sector basis. In switching the keyinformation at the pre-set timing, whether or not switching is to bemade, the switching period or the switching sequence of the plural keyinformation items may also be used as the key for further raising theciphering level, ease or difficulty of ciphering, or difficulties indeciphering.

[0057] The construction of the circuits 13 to 18 and specified examplesof ciphering will be explained.

[0058] First, the sector forming circuit 13 may be designed forinterleaving even and odd bytes, as shown for example in FIG. 2. Thatis, in FIG. 2, an output of the interfacing circuit 12 of FIG. 1 is sentto a two-output changeover switch 31, an output of which is sent via aneven/odd interleaver 33 to a sector forming circuit 34 and the otheroutput of which is directly sent to the sector-forming circuit 34. Thesector-forming circuit 34 collects the input data in terms of 2048 bytesas unit to form one sector. The switching operation of the changeoverswitch 32 of the sector forming circuit 13 is controlled by a 1-bitcontrol signal operating as the key. The even/odd interleaver 33distributes one sector of the input data, having even bytes 36 a and oddbytes 36 f arrayed alternately as shown in FIG. 3A, into an even dataportion 37 a and an odd data portion 37 b, as shown in FIG. 3, andoutputs these data portions. Moreover, a specified portion 39 in asector may be specified by the key information and data in only thisspecified portion 39 may be distributed into an even data portion 39 aand an odd data portion 39 b. In this case, the manner of specifying theportion 39 may be designed to be selected in plural methods for furtherincreasing the number of the alternatives of the key information forraising the ciphering level.

[0059] The scrambling circuit 14 can use a scrambler of the so-calledparallel block synchronization type employing a 15-bit shift register,as shown for example in FIG. 4. To a data input terminal 35 of thescrambler is supplied data from the sector forming circuit 13 in anorder in which the least significant bit (LSB) comes temporally first,that is in the so-called LSB first order. A 15-bit shift register 14 afor scrambling is associated with an exclusive-OR (EXOR) circuit 14 bfor applying the feedback in accordance with the generating polynominalx¹⁵+x+1. Thus, a pre-set value or an initial value as shown in FIG. 5 isset on the 15-bit shift register 14 a. Meanwhile, the selection numberof the pre-set value of FIG. 5 can be switched on the sector basis inassociation with, for example, the value of the lower four bits of thesector address. Output data of the shift register 14 a and input data ata terminal 35 are ExORed by the ExOR circuit 14 c so as to betaken outat a terminal 14 d and sent to the header appendage circuit 15 of FIG.1.

[0060] The generating polynominal and the pre-set value (initial value)may be varied in accordance with the key information, such as thepre-set identification number. That is, for varying the generatingpolynominal, the configuration as shown in FIG. 6 may be used. In FIG.6, outputs of the respective bits of the 15-bit of the shift register 14a are sent to fixed terminals of the changeover switch 14 f controlledby, for example, 4-bit control data from a control terminal 14 g. Anoutput of the changeover switch 14 f is sent to the ExOR circuit 14 b.By changing the control data of the control terminal 14 g, it becomespossible to change the value of n in the generating polynominalx¹⁵+x^(n)+1 . For changing the pre-set value, the pre-set values of thepre-set value table of FIG. 5 may be processed with arithmeticaloperation with each byte value of the 16-byte identificationinformation. The identification information may be enumerated by theidentification information proper to the medium, the produceridentification information, dealer identification information, theidentification information proper to the recording apparatus or theencoder, the identification information proper to the medium producingapparatus, the territory information, or the identification informationfurnished from outside. The above information may be used in combinationwith one another or with the other information. The configuration forvarying the generating polynominal is not limited to the configurationof FIG. 6, such that the number of taps or stages of the shift registermay be changed as desired.

[0061] The header appendage circuit 15 is now explained.

[0062]FIG. 7 shows a specified example of the sector format. Each sectoris made up of a 2048-byte user data area 41, to which are appended a4-byte synchronization area 42, a 16-byte header area 43 and a 4-byteerror detection code (EDC) 44. The error detection code of the errordetection doe area 44 is made up of 32-bit CRC code generated for theuser data area 41 and the header area 43. Ciphering in the headerappendage circuit 15 may be performed on a synchronization signal, thatis a so-called data sync, a header address or CRC.

[0063] As an example of ciphering the sector synchronization signal ordata sync, if byte patterns allocated to respective bytes of the 4-bytesync area 42 are denoted by A, B, C and D in FIG. 8, the contents ofthese four bytes may be shifted or rotated on the byte basis using the2-bit key information. That is, by switching to ABCD, BCDA, CDAB or toDABC for the 2-bit key of 0, 1, 2 or 3, respectively, sectorsynchronization cannot be achieved failing the key data coincidence,such that regular reproduction cannot be realized. For the byte patternsA to D, character codes of ISO646, for example, may be used.

[0064] In the header region 43, there are formed respective layers forCRC 45, as a so-called redundancy cyclic code, the copying information46 for copying permission/non-permission, or management of the copyinggeneration, a layer 47 indicating a specified layer of a multi-layereddisc, an address 48 and a spare 49, as shown in FIG. 9. Ciphering can bemade by bit scrambling, herein bit-based transposition, on 32 bits ofthe address 48. If x¹⁶+x¹⁵+x²+1 is used as a generating polynominal forthe CRC 45, ciphering can also be made by varying 15 bits forx^(5{tilde over ()})x responsive to the key in place of the second termx¹⁵ and the third term x². Ciphering can also be made by processing 16bits of the CRC 45 and the key information by arithmetical operations.

[0065] The key information may be enumerated by the identificationinformation proper to the medium, the producer identificationinformation, dealer identification information, the identificationinformation proper to the record apparatus, encoder or the mediumproducing apparatus, the territory information, or the identificationinformation furnished from outside. The above information may be used incombination with one another or with the other information.

[0066]FIGS. 10 and 11 illustrate a specified embodiment of the errorcorrection encoding circuit 16.

[0067] In FIGS. 10 and 11, data from a header appendage circuit 15 ofFIG. 1 is fed via an input terminal 51 to a C1 encoder 52. In thepresent specified embodiment, each frame of error correction andencoding is made up of 148 byte or 148 symbol data. The digital data atthe input terminal 51 are collected every 148 bytes and sent to a C1encoder 52 as a first encoding unit. In the C1 encoder 52, an 8-byteparity is appended, and the resulting data is sent via a delay circuit53 for interleaving to a C2 encoder 54 as a second encoding unit. The C2encoding unit 54 appends to the data a 14-byte Q-parity which is fedback via a delay circuit 55 to the C1 encoder 52. From the C1 encoder52, 170 bytes containing P and Q parities are taken out and outputtedvia the delay circuit 56 and a re-arraying circuit 57 having an inverter57 a at an output terminal 58 so as to be sent to a modulation circuit17 of FIG. 1.

[0068] For ciphering in the above-described error correction encodingcircuit, it may be contemplated to make selection as to whether or notinverters should be inserted responsive to the ciphering key informationevery byte of the inverting portion 57 a in the re-arraying circuit 57.That is, although 22-byte P- and Q-parities are inverted by theinverters of the inverter portion 57 a of the re-arraying circuit 57 inthe basic configuration, some of these inverters may be eliminated or anumber of inverters may be inserted on the C1 data for inverting outputparities.

[0069] When performing such data conversion, the probability ofimpossible error correction is varied depending on the degree ofdifference from the basic configuration, such that, if such differenceis small, the probability of error occurrence at the ultimate reproducedoutput is only slightly increased, whereas, if there are manydifferences, error correction becomes difficult on the whole such thatreproduction becomes nearly impossible. For example, in the case of theC1 encoder, the distance as an index specifying the error correctioncapability is 9, so that error detection and correction is possible upto 4 bytes at the maximum and, if there is an erasure point, correctionup to 8 bytes at the maximum is possible. Thus, if there are five ormore differences, correction becomes always impossible with the C1 code.If there are four differences, a delicate state of correction becomingimpossible by at least one other error occurs. As the difference isdecreased from three through two to one, the probability of errorcorrection becoming feasible increases in this order. If this isutilized, the state of reproduction in which in case of furnishing audioor video software reproduction is possible to a certain extent but isnot impeccable and sometimes perturbed can be crated positively. Thiscan be exploited for informing the user of only the epitome of thesoftware.

[0070] In this case, it is possible to use such a method in which thesites of change of the inverters are prescribed at, for example, twosites, a method in which the sites of changes are selected at randomdepending on the key information and the smallest number of the sites ofchange are limited to two sites, or a method consisting in thecombination of the two methods.

[0071] The positions of insertion or modification of the inverters arenot limited to those in the re-arraying circuit 57 in FIGS. 10 and 11,but any arbitrary positions upstream or downstream of the C1 encoder 52or the combinations thereof may also be used. In case there are pluralpositions, different keys may be used. As for the data conversion, bitaddition or the like logical operations may be used in place of usinginverters, data may be transposed depending on the key information forciphering, or data may be replaced depending on the key information forciphering. Of course, a variety of ciphering techniques, such asconversion by shift registers or by various function processing, can beused alone or in combination.

[0072]FIG. 12 shows another specified embodiment of the error correctionencoding circuit 16 in which a set of exclusive-OR (ExOR) circuits 61 isinserted downstream of the inverter 57 a within the re-arraying circuit57 and in which another set of exclusive-OR circuits 61 is insertedupstream of, that is on the input side of the C1 encoder 52.

[0073] Specifically, the set of the ExOR circuits 61 perform dataconversion of EXOR operation on 170-byte data taken out from the C1encoder 52 via the delay circuit 56 and the inverter portion 57 a of there-arraying circuit 57, that is on information data C_(170n+169)^({tilde over ()}) _(C170n+22) and parity data P_(170n +21)^({tilde over ()})P_(170n+14), Q_(170n+13) ^({tilde over ()})Q_(170n),while the set of the ExOR circuits 66 perform data conversion of ExORoperation on 148-byte input data B_(148n)^({tilde over ()})B_(148n+147). The ExOR circuits, used in these set ofthe ExOR circuits 61, 66, Ex-OR 1-byte or 8-bit input data and pre-set 8bit data specified by a 1-bit control data. 170 and 148 of these 8-bitExOR circuits (equivalent to an inverter circuit if the pre-set 8-bitdata are all zero) are used for the set of the ExOR circuits 61, 66,respectively.

[0074] In FIG. 12, the 170-bit key information is sent to a terminal 62and routed via a so-called D- latch circuit 63 to each of the 170 ExORcircuits in the set of the ExOR circuits 61. The D-latch circuit 63 isresponsive to the 1-bit ciphering control signal supplied to an enablingterminal 64 to switch between sending the 170-bit key information fromthe terminal 62 directly to the set of the ExOR circuits 61 and settingall of the 170 bits to “0”. Of the 170 ExOR circuits of the set of theExOR circuits 61, the ExOR circuit fed with “0” from the D-latch circuit63 directly output data from the inverter portion 57 a in there-arraying circuit 57, while the ExOR circuit fed with “1” from theD-latch circuit 63 inverts and outputs data from the inverter portion 57a in the arraying circuit 57. In case of all-zero, data from theinverter portion 57 a in the re-arraying circuit 57 is directlyoutputted. The set of the ExOR circuits 66 is similar to the set of theExOR circuits 61 except that it includes 148 ExOR circuits and has thekey information of 148 bits. Thus, the 148-bit key information suppliedto a terminal 67 is sent via a D-latch circuit 68 to each of the set ofthe ExOR circuits in the set of the ExOR circuits. The D-latch circuit68 is switched to 148-bit key information or all-zeros by the cipheringcontrol signal of an enabling terminal 69.

[0075] In the circuit of FIG. 12, the set of the ExOR circuits 61perform data conversion of ExOR operation on 170-byte data taken outfrom the C1 encoder 52 via the delay circuit 56 and the inverter portion57 a of the re-arraying circuit 57, that is on information dataC_(170n+169) ^({tilde over ()})C_(170n+22) and parity data P_(170n+21)^({tilde over ()})P_(170n+14), Q_(170n+13)^({tilde over (o0 )})Q_(170n). Alternatively, the set of the ExORcircuits 61 may be designed to perform data conversion on 148-byteinformation data C_(170n+169) ^({tilde over ()})C_(170n+22), dependenton the 148-bit key information, without performing data conversion onthe parity data.

[0076] With the circuit of FIG. 12, the operation and effect similar tothose of FIGS. 10 and 11 may be realized. It is also possible to use oneof the ExOR circuits 61 and 66 or to use the selection of one or both ofthe ExOR circuits as the ciphering key.

[0077] The key information may be enumerated by the identificationinformation proper to the medium, producer identification information,dealer identification information, identification information proper tothe record apparatus, encoder or the medium producing apparatus,territory information, or the identification information furnished fromoutside. The above information may be used in combination with oneanother or with the other information.

[0078] In place of the ExOR circuits 61 and 66 as the data conversionmeans, AND, OR, NAND, NOR or inverter circuits may also be used as theabove data conversion means. In addition to performing logicalprocessing by the 1-bit key information or the key data on the 8-bitbasis, logical processing may also be performed on the 8-bit informationdata. Alternatively, the AND, OR, ExOR, NAND, NOR or inverter circuitsmay be used in combination for respective ones of the 8 bitscorresponding to 1 word of the information data. In this case, 148×8 bitkey data is used for 148-byte data, that is 148×8 bit data. Moreover, ifthe AND, OR, ExOR, NAND, NOR or inverter circuits are used incombination, these combinations themselves may also be used as the key.Various ciphering techniques, such as conversion by shift registers orvarious function processing may, of course, be used such that these mayalso be used in combination.

[0079] Although an example of cross-interleaving type error correctioncode has been explained in the first embodiment, it may also be appliedto a product code, as will be explained later as a second embodiment ofthe present invention.

[0080] Referring to FIG. 13, ciphering by the modulation circuit 17 ofFIG. 1 is now explained. In this figure, data from the error correctioncoding circuit 16 is fed every 8 bits (one byte) to a terminal 71, whilethe 8-bit key information is fed to an input terminal 72. These 8-bitdata are fed to an ExOR circuit 73, as an example of the logicalprocessing circuit, for performing an Ex-OR operation. An 8-bit outputof the ExOR circuit 73 is sent to a modulator of a pre-set modulationsystem, such as an 8-16 conversion circuit 74, for conversion to 16channel bits. An example of the 8-16 conversion system by the 8-16conversion circuit 74 is a called EFM plus modulation system.

[0081] Although the ciphering employing the 8-bit key information isperformed prior to data modulation, the number of bits of the keyinformation is not limited to 8, while the input-output correlation of aconversion table used for 8-16 conversion may be varied responsive tothe key information. For the key information, the identificationinformation proper to the record medium as described above may, ofcourse, be employed.

[0082] The synchronization appendage circuit 18 is now explained.

[0083] The synchronization appendage circuit 18 takes synchronization,using four sorts of synchronization words S0 to S3 shown in FIG. 14, interms of frames of the 8-to-16 modulation as unit. For example, to 85data symbols or 1360 channel bits as one frame of the 8-to-16 modulationis added a synchronization word of 32 channel bits, this frame isstructured by association with the C1 or C2 code and the synchronizationword of a leading frame of the C1 codestring is caused to differ fromthe synchronization word of another frame for producing the four sortsof the synchronization words S0 to S3. These synchronization words S0 toS3 have respective two synchronization patterns a and b depending on thestates of “1” or “0” of the directly previous word, the so-calleddigital sum or the dc value.

[0084] Selection of these four synchronization words S0 to S3 can bechanged depending on two bits of the key information 75, using thecircuit shown for example in FIG. 15, for the purpose of effecting theciphering. That is, respective bits of two-bit data 76 designating thefour synchronization words S0 to S3 and respective bits of the 2-bit keyinformation 75 are ExORed by two ExOR circuits 77, 78 for producing anew synchronization word designating data 79. This modifies the mannerof using the synchronization word in the above-described frame structureor the position of using various sorts of the synchronization words inthe above-described frame structure for the purpose of effecting theciphering.

[0085] It is also possible to increase the number of sorts of thesynchronization word and to determine the manner of taking out the foursorts of the synchronization words from among these synchronizationwords depending on the ciphering key. The aforementioned identificationinformation proper to the record medium may be used as this keyinformation.

[0086]FIG. 16 shows a disc-shaped record medium 101, such as an opticaldisc, as an example of the record medium. This disc-shaped record medium101 has a center aperture 102 and has formed therein a lead-in area 103,as a table-of-contents (TOC) area or a program management area, aprogram area 104 for recording program data and a program end area or alead-out area 105, looking from the inner rim towards the outer rimthereof. In an optical disc for reproducing audio signals or videosignals, audio or video data is recorded in the program area and thetime information for the audio or video data are managed by the lead-inarea 103.

[0087] As part of the key information, the identification informationwritten in an area other than the program area as the data recordingarea may be used as part of the key information. Specifically, theidentification information, including the identification information,such as the production number proper to the record medium,identification information for the producer, identification informationfor the dealer, identification information proper to the recordingdevice or the encoder or identification information proper to the devicefor producing the record medium, such as a cutting machine or a stamper,may be written the lead-in area 103 as the TOC area or in the lead-outarea 105. A signal obtained on ciphering in at least one and preferablytwo of the above-mentioned six circuits 13 to 18 is recorded in theprogram area 104 as the data recording area. For reproduction, the aboveidentification information may be used for deciphering. Theidentification information may also be written physically or chemicallyinwardly of the lead-in area 103 and read out during reproduction so asto be used as the key information for decoding.

[0088] Referring to FIG. 17, preferred embodiments of the datareproducing method and the data reproducing apparatus according to thepresent invention will be explained.

[0089] In FIG. 17, the disc-shaped record medium 101, as an example ofthe record medium, is run in rotation by a spindle motor 108 so that therecording contents thereof are read out by a reproducing head device109, such as an optical pickup.

[0090] The digital signals read out by the reproducing head device 109is sent to a TOC decoder 111 and to an amplifier 112. From the TOCdecoder 111, the identification information, including theidentification information, such as the production number proper to therecord medium, identification information for the producer,identification information for the dealer, identification informationproper to the recording device or the encoder or identificationinformation proper to the device for producing the record medium, suchas a cutting machine or a stamper, are read out so as to be used as atleast a portion of the key information for decoding the ciphering. Theidentification information proper to the reproducing device or theidentification information from outside may be outputted from a CPU 122in the reproducing device so as to be used as at least a portion of thekey information. The identification information from outside includesthe identification information received via the communication network ortransmission path and the identification information obtained on readinga so-called IC card, ROM card, a magnetic card or an optical card.

[0091] The digital signal taken out from the reproducing head device 109via amplifier 112 and a phase-locked loop (PLL) circuit 113 is sent to asynchronization separation circuit 114 for separation of thesynchronization signal appended by synchronization appendage circuit 18of FIG. 1. The digital signal from the synchronization separationcircuit 114 is sent to a demodulation circuit 115 for performing anoperation which is the reverse of the modulation performed by themodulation circuit 17 of FIG. 1. Specifically such operation isconverting 16 channel bits into 8 bit data. The digital data from thedemodulation circuit 115 is sent to an error correction decoding circuit116 for performing decoding as a reverse operation of the encodingperformed by the error correction encoding circuit 16 of FIG. 1. Thedecoded data is resolved into sectors by a sector resolution circuit 117and a header at the leading end of each sector is separated by theheader separation circuit 118. The header resolution circuit 117 and theheader separation circuit 118 are counterpart device's of the sectorforming circuit 13 and the header appendage circuit 15 of FIG. 1,respectively. A descrambling circuit 119 then performs descrambling as areverse operation of the scrambling performed by the scrambling circuit14 of FIG. 1 so that reproduced data is outputted via an interfacingcircuit 120 at an output terminal 121.

[0092] It should be noted that ciphering has been performed duringrecording in at least one of the sector forming circuit 13, scramblingcircuit 14, header appendage circuit 15, error correction encodingcircuit 16, modulation circuit 17 and the synchronization appendagecircuit 18, such that a deciphering operation is required in thereproducing side circuits 114 to 119 as counterpart devices of theciphering circuits. That is, if ciphering is performed by the sectorforming circuit 13 of FIG. 1, it is necessary for the sector resolutioncircuit 117 to perform ciphering using the key information used forciphering. Similarly, the deciphering by the descrambling circuit 119,by the header separation circuit 118, by the error correction decodingcircuit 116, by the demodulation circuit 115 and by the synchronizationseparation circuit 114 become necessary in association with theciphering by the scrambling circuit 14, header appendage circuit 15,error correction encoding circuit 16, modulation circuit 17 and by thesynchronization appendage circuit 18 of FIG. 1, respectively.

[0093] The deciphering by the synchronization separation circuit 114 isperformed by detecting the manner of using a plurality of, for example,four, different sorts of the synchronization words or the position ofuse of the various synchronization words in a frame structure, modifiedin accordance with the key information for ciphering, as explained withreference to FIGS. 14 and 15.

[0094] In the deciphering operation by the demodulation circuit 115, the8-bit data, sent from the synchronization separation circuit 114 to a16-to-8 conversion circuit 131 so as to be converted from the 16 channelbits, are sent to an. ExOR circuit 132, as a counterpart circuit of theExOR circuit 73 of FIG. 13, so as to be Ex-ORed with the 8-bit keyinformation from a terminal 133, for restoring data corresponding to the8-bit data supplied to the input terminal 71 of FIG. 13, as shown inFIG. 18. The restored data is sent to the error correction decodingcircuit 116.

[0095] The error correction decoding circuit 116 performs a reverseoperation of the error correction encoding shown in FIGS. 10 and 11 bythe constitution of FIGS. 19 and 20.

[0096] Referring to FIGS. 19 and 20, demodulated data from thedemodulation circuit 115 are sent, in terms of 170 bytes or 170 symbolsas units, via a re-arraying circuit 142 having an inverter 142 a and viaa delay circuit 143, to a C1 decoder 144 as a first decoder. Of the 170bytes of data supplied to this C1 decoder 144, 22 bytes are P paritydata and Q parity data. The C1 decoder 144 performs decoding using theseparity data. The C1 parity data outputs 170 byte data via a delaycircuit 145 to a C2 decoder 146 as a second decoder where errorcorrection and decoding are performed using these parity data. Outputdata of the C2 decoder 146 is sent to a delay-C1 decoding circuit 140 ofFIG. 19. This circuit is similar to the delay circuit 143 and the C1decoder 144 and repeatedly performs the operation similar to thatperformed by the delay circuit 143 and the C1 decoder 144 for performingerror correction and decoding. In the embodiment of FIG. 20, delay-C1decoding circuit 140 is shown as a delay circuit 147 and a C3 decoder148 as a third decoder. The delay circuit 147 and the C3 decoder 148 orthe delay-C1 decoding circuit 140 perform ultimate error correction anddecoding so that 148-byte data devoid of parity is outputted at anoutput terminal 149. The 148-byte data corresponds to the 148-byte dataentering the C1 decoder 52 of FIG. 11.

[0097] If ciphering has been performed in the inverter portion 57 a ofthe re-arraying circuit 57 of the error correction encoding circuit ofFIGS. 10 and 11, it is necessary for the inverter portion 142 a in there-arraying circuit 142 of the error correction and decoding circuit ofFIGS. 19 and 20 to perform corresponding deciphering. It is of coursenecessary to perform deciphering as a reverse operation of the varioussorts of ciphering explained with reference to FIGS. 10 and 11.

[0098]FIG. 21 shows an illustrative structure of the error correctiondecoding circuit as a counterpart of the illustrative structure of theerror correction encoding circuit shown in FIG. 12.

[0099] Referring to FIG. 21, a set of ExOR circuits 151 are inserted onan input side of the inverter portion 142 a of the re-arraying circuit142 and on an input side of the delay circuit 143, in association withthe set of ExOR circuits 61 inserted on the output side of the inverterportion 57 a of the re-arraying circuit 57 of FIG. 12, while a set ofExOR circuits 156 are inserted on the output side of the C1 decoder 148in association with the ExOR circuits 66 inserted on the input side ofthe C1 encoder 52 of FIG. 12.

[0100] These Ex-OR circuit sets 151, 156 are configured for dataconversion for decoding the data conversion performed by the ExORcircuits sets 61, 66 of FIG. 12. Of these, the set of the ExOR circuits151 are made up of, for example, 170 8-bit ExOR circuits, while the setof the ExOR circuits 156 are made up of, for example, 148 8-bit ExORcircuits. If data conversion responsive to the key information has beendone for the 148-byte information data excluding the parity data by theExOR circuits 61 of the recording side error correction encoding circuitof FIG. 12, the set of the ExOR circuits 151 are naturally constitutedby 148 8-bit ExOR circuits.

[0101] To a terminal 152 of FIG. 21 is supplied the 170-bit keyinformation corresponding to the key information supplied to theterminal 62 of FIG. 12. The key information is supplied via a D-latchcircuit 153 to each of 170 ExOR circuits within the set of the ExORcircuits 151. The D-latch circuit 153 is switched, responsive to the1-bit ciphering control signal supplied to an enabling terminal 154,between sending the 170-bit key information from the terminal 152directly to the set of ExOR circuits 151, and setting the 170 bits to“0” in their entirety (all-zero). On the other hand, the set of ExORcircuits 156 are similar to the set of the ExOR circuits 151 except thatthe set of ExOR circuits 156 has 148 ExOR circuits 151 and has the148-bit key information similarly to the key information supplied to theterminal 12 of FIG. 12. The 148-bit key information supplied to aterminal 157 is sent via a latch circuit 158 to each of the 148 ExORcircuits 156 via D-latch circuit 158. The D-latch circuit 158, in turn,is switched responsive to the ciphering control signal from an enablingterminal 159 between the 148-bit key information and all-zero.

[0102] By employing the ExOR circuits or the inverter of the errorcorrection circuit, it becomes possible to realize simple andsignificant ciphering. Moreover, by controlling the number of theinverters, normally non-reproducible data of the ciphering level or databecoming non-reproducible in a worsened error state can be coped withresponsive to the demand for security level. That is, by controlling thenumber of the inverters or the ExOR circuits, control can be done insuch a manner that reproduction becomes possible and impossible for thebetter and worse error states, respectively. Moreover, the reproduciblestate that cannot be recovered by error correction by itself can also beproduced. As for the ciphering key, the number of bits can even reach100 or more per ciphering site as in the above illustrated embodimentand hence ciphering with the large number of bits of the key becomespossible thus improving data security. Moreover, by implementing theerror correction encoding circuit and the error correction decodingcircuit within an LSI or IC chip hardware, accessing to the recordmedium can be made more difficult from the users in general, thus againraising data security.

[0103] The sector resolution circuit 117 performs so-calleddeinterleaving, that is a reverse operation to the even or oddinterleaving if ciphering by such even or odd byte interleaving has beendone for recording by the sector forming circuit 13, as explained withreference to FIGS. 2 and 3.

[0104] The header separation circuit 118 performs correspondingdeciphering if the ciphering explained with reference to FIGS. 7 to 9,that is data sync byte pattern transposition representing sectorsynchronization, address change or CRC change, has been done duringrecording by the header appendage circuit 15.

[0105]FIG. 22 shows an illustrative embodiment of the descramblingcircuit 119. To a terminal 161 is fed digital data from the headerseparation circuit 118 of FIG. 17. Digital data from the terminal 161 isdescrambled by a scrambler 163 configured as shown in FIG. 4 so as to betaken out at an output terminal 164. Deciphering can be performed bychanging a polynomial 165 and a pre-set value or the initial value 166as explained with reference to FIG. 4 for the scrambler 163 independence upon the ciphering key information from an authorizationmechanism 171. The authorization mechanism 171 generates the cipheringkey information, depending upon the contents of the copying information46 of the header information 167, identification information proper tothe record medium or to the reproducing apparatus, the commonidentification information 173 proper to the producer or the dealer orthe external identification information 174 supplied from outside forcontrolling the generating polynominal cib165 or the pre-set value 166depending on the key information.

[0106] The information as to n which of these circuits 114 to 119 thedeciphering is required may prove to be the key information forciphering, as discussed previously. Moreover, the ciphering keyinformation may be switched in a pre-set period, for example, everysector. The extent of ease or difficulty in ciphering is increased byusing whether or not switching is to be made, or the switching period,as the key.

[0107] By combining the producer identification information, dealeridentification information or device identification information with thecopying protection information or charging information, set separately,as described above, for ciphering data, and recording the ciphered data,prevention of copying, pirate edition or illicit use can be realized onthe physical format level. In addition, the information concerning thedata security function, copying permit/non-permit information or thecharging/charge-free information is implemented on a record medium or ina physical format of the recording/reproducing system.

[0108] That is, by pre-recording the security/charging information onthe record medium, and by combining it with data ciphering using therecording/non-recording information for the record medium, copyingprevention and prevention of illicit use can be realized by a simplifiedstructure. Decoding can be made difficult by latent incorporation in thephysical format. The structure is safe against dump copying since itremains in the ciphered state. The structure can be varied on the sectorbasis, on the file basis, on the zone basis or on the layer basis.Moreover, key control can be done by communication, IC card or by aremote controller. Hysteresis can also be left against pirating.

[0109] The second embodiment of the present invention is now explained.

[0110] The second embodiment is a partial modification of the firstembodiment described above. The overall structure is as shown in FIG. 1.Only the modified portions of the circuits 13 to 18 of the configurationof FIG. 1 are now explained.

[0111] The sector forming circuit 13 of FIG. 1 can be configured as inthe first embodiment described above. However, the scrambling circuit 14is configured as shown in FIG. 23.

[0112] In the scrambling circuit 14, shown in FIG. ,23, data from thesector forming circuit 13 of FIG. 1 is supplied in a sequence in whichthe least significant bit (LSB) comes temporally first, that is in theLSB first order, to the data input terminal 35. A 15-bit shift register14 a for scrambling is configured so that feedback by the generatingpolynominal x¹⁵+x⁴+1 will be applied using an exclusive-OR (ExOR)circuit 14 b, while a pre-set value or an initial value as shown in FIG.24 is set in the 15-bit shift register 14 a. The selection numbers ofthe pre-set values shown in FIG. 24 are selected so that the pre-setvalues can be switched on the sector basis in association with, forexample, the values of the lower 4 bits of the sector address. Outputdata of the shift register 14 a and input data from the terminal 35 areEx-ORed by the ExOR circuit 14 c, an output of wich is outputted at anoutput terminal 14 d so as to be sent to the header appendage circuit 15of FIG. 1.

[0113] The pre-set value (initial value) can be varied depending on thekey information such as the pre-set identification number. That is, thepre-set values of the 16-byte identification information of the pre-setvalue table of FIG. 24 can be logically processed with respective bytevalues of the 16-byte identification information. The identificationinformation in this case may include the identification information suchas the production number proper to the record medium, identificationinformation for the producer, identification information for the dealer,identification information proper to the recording device or the encoderor identification information proper to the device for producing therecord medium, territory information, identification informationsupplied from outside, alone or in combination. The above information ofvarious sorts may also be used in combination with other sorts of theinformation. The logical processing includes exclusive OR (ExOR),logical product (AND), logical sum (OR) or shifting.

[0114] The sector format for the second embodiment may be configured asshown for example in FIG. 25.

[0115] As shown in FIG. 25, each sector is made up of 12 rows each beingof 172 bytes, totaling at 2064 bytes, of which 2048 bytes represent maindata. At a leading position of the first one of the 12 rows are arrayeda 4-byte identification data (ID), a 2-byte ID error detection code(IED) and 6-byte reserve data (RSV), in this order. At a terminalposition of the last row is arrayed a 4-byte error detection code (EDC).

[0116] As shown in FIG. 26, the 4-bytes of the identification data (ID)are made up of the first byte (bits b31 to b24) formed by the sectorinformation and the remaining three bytes (bits b23 to b0) formed by thesector numbers. The sector information is made up of a 1 bit of thesector format type, a 1 bit of the tracking method, a 1 bit ofreflectance, a 1 bit of the spare information, 2 bits of the area typeand 2 bits of the layer number.

[0117] The header appendage circuit 15 of FIG. 1 performs transposition,that is bit-based scrambling, on the 14 bits of the sector number in theidentification data (ID) in the sector format, responsive to the keyinformation, for effecting the ciphering. In addition, the generatingpolynominal of the 2-byte ID error detection code (IED) or thegenerating polynominal of the 4-byte error detection code (EDC) can bemodified depending on the key information or logically processed withthe key information for effecting the ciphering.

[0118] The error encoding correction circuit 16 of FIG. 1 may beconfigured as shown in FIG. 27. For encoding, product code or the blockcode as shown in FIG. 28 is used.

[0119] Referring to FIG. 27, data from the header appendage circuit 15shown in FIG. 1 is supplied to an input terminal 210. This input data issupplied to a PO encoder 211 as a first encoding unit. Input data to thePO encoder 211 is 172 bytes×192 rows, or B_(0.0) to B_(191,172). The POencoder 211 appends an RS outer code (PO) of RS (208,192,17) as 16-byteReed Solomon code (RS code) to each of 192 bytes of each of 172 columns,as shown in FIG. 28. Output data of the PO encoder 211 are sent via thedata conversion circuit for ciphering 212 as described above to aninterleaving circuit 213 to from interleaved data which is sent to a PIencoder 214. The PI encoder 214 appends an RS inner code (PI) of RS(182,172,11) (RS code) to each row of 172 bytes of the 172 bytes×208rows. Thus the PI encoder 214 outputs data of 182 bytes×208 rows. Thisoutput data is outputted at an output terminal 216 via a data conversioncircuit 215 for ciphering as described above.

[0120] Since the PO encoder 211 appends the 16-byte PO parity to the192-byte input data for each column to output 208-byte data, the dataconversion circuit 212 performs data conversion as described above onthe 16-byte parity or 208-byte data in their entirety for effecting theciphering. This data conversion may be made responsive to the keyinformation supplied via a terminal 218. Since the data conversioncircuit 215 appends 10-byte PI parity to 172-byte data of each row foroutputting 182-byte data, the data conversion circuit 215 can performciphering by effecting data conversion on the 10-byte data or on the182-byte data in their entirety. This data conversion can be performedresponsive to the key information supplied via the terminal 219 asdescribed previously.

[0121] The above data conversion may be performed by arranging aninverter at a pre-set position, by selectively inverting data by the setof the ExOR circuits responsive to the key information or by using theAND, OR or NAND circuits. In addition to the logical processing on the8-bit information data by the 1-bit key information data or by key data,logical processing may be performed on the 8-bit information data by the8-bit key information data, or the AND, OR, ExOR, NAND, NOR or invertercircuits may be used in combination for each of 8 bits making up a wordof the information data. Of course, a variety-of ciphering techniques,such as conversion by shift registers or function processing may beapplied alone or in combination. If the AND, OR, ExOR, NAND, NOR orinverter circuits are used in combination, the combination itself may beused as the key. Moreover, in addition to the logical precessing,transposition of changing data positions or substitution of substitutingdata values may also be used for data conversion. Of course, a varietyof ciphering techniques, such as conversion by shift registers orfunction processing, may be applied alone or in combination.

[0122] The 182 bytes×208 rows of data, resulting from error correctionencoding, are interleaved with respect to rows and separated into 1613-row groups each of which is associated with a recording sector. Eachsector, made up of 182 bytes×13 row, totaling at 2366 bytes, ismodulated and two synchronization codes SY are appended per row as shownin FIG. 29. For modulation, 8-to-16 conversion is used as in theabove-explained first embodiment. Each row is divided into two syncframes, each of which is made up of a 32-channel-bit synchronizationcode SY and a 1456-channel-bit data portion. FIG. 29 shows a datastructure for one sector obtained on modulation and appendage ofsynchronization data. The 38688 channel bits of each sector, shown nFIG. 29, corresponds to 2418 bytes prior to modulation.

[0123] The modulated output signal of FIG. 29 uses eight sorts of thesynchronization codes SY0 to SY7. These synchronization codes SY0 to SY7represent synchronization patterns of FIG. 30(a) and FIG. 30(b) for the8-16 conversion states 1, 2 and for the 8-16 conversion states 3 and 4,in dependence upon the above-described 8-16 conversion states,respectively.

[0124] The selection of the eight sorts of the synchronization codes SY0to SY7 may be changed responsive to the 3-bit key information foreffecting the ciphering. That is, respective bits of three-bit data 221designating the eight sorts of the synchronization codes SY0 to SY7 andthe respective bits of the 3-bit key information 222 are Ex-ORed by thethree ExOR circuits 223, 224 and 225 to produce-new synchronization codedesignating data 226. This modifies the manner of using thesynchronization code in the above frame structure or the position ofusing the various synchronization codes in the frame structure to effectthe ciphering. Of course, data of the three bits may be transposed,substituted or converted by a shift register or by a function conversiondepending on the key information

[0125] The basic structure of a reproducing side, as the counterpart ofthe recording side structure of the above-described second embodiment ofthe present invention, is similar to that shown in FIG. 17, and areverse operation modified in meeting with modified portions in thesecond embodiment is performed. For example, the reverse operation as acounterpart of the error correction encoding shown in FIG. 27 can beimplemented by an error correction decoding circuit shown n FIG. 32.

[0126] In this figure, data of the product code of 182 bytes×208 rows ofFIG. 28, corresponding to an output of the output terminal 216 of FIG.27, that is an output signal of the demodulating circuit 115 of FIG. 17,is supplied to an input terminal 230. This data from the input terminal230 is sent to a data conversion circuit 231 where a reverse operationof the operation performed by the data conversion circuit 215 of FIG. 27is performed. Output data of the data back-conversion circuit 231 issent to a PI (inner code) decoder 232 where the decoding as the reverseoperation of the operation performed by the PI encoder 214 of FIG. 27,that is error correction employing the PI code, is performed forproducing 172 bytes×208 rows of data shown in FIG. 28. Output data ofthe PI decoder 232 is processed by an operation which is the reverse ofthe operation performed by the data conversion circuit 213 andsubsequently sent to a PO (outer code) decoder 235. The PO decoder 235performs a decoding operation as a reverse operation of the operation bythe PO encoder 211 of FIG. 27, that is error correction employing the POcode, for taking out the original 172 bytes×182 rows of data of FIG. 28at an output terminal 236. If the key information is used for dataconversion by the data conversion circuits 212, 215 of FIG. 27, the keyinformation supplied to each of the terminals 218, 219 may be suppliedto terminals 239, 238 of the data back-conversion circuits 234, 231 ofFIG. 32 for effecting data back-conversion depending on the keyinformation.

[0127] The favorable effect f the above-described second embodiment ofthe present invention is similar to that of the above-mentioned firstembodiment.

[0128] In the above-described embodiment of the data recording methodaccording to the present invention, input data is processed withciphering in at least one of the sector forming step of dividing inputdigital data in terms of the pre-set data amount, a header appendagestep of appending the header, an error correction encoding step, amodulating step for modulation in accordance with a pre-set modulationsystem, and a synchronization appendage step of appending thesynchronization pattern, and the resulting ciphered data is outputted,so that the particular step in which the ciphering has been made alsobecomes the key for ciphering, thus raising the degree of ease ordifficulty in ciphering. The scrambling step of randomizing the data foreliminating the same pattern may also be included among the cipheringsteps. There is also a merit that ciphering can be realized easily bysimply modifying part of the preexisting configuration. These effectscan be realized with the data recording apparatus, record medium, datareproducing method or data reproducing apparatus.

[0129] Since data conversion is done on at least a portion of datahandled during error correction encoding, depending on the keyinformation for ciphering, ciphering of a desired level between thelevel for which data restoration is possible to some extent by errorcorrection encoding and a level for which data restoration is notpossible can be realized. This renders possible such control in whichreproduction is possible or is not possible for an acceptable errorstate or for an unacceptable error state, thus enabling accommodationcomplying with the usage of data or security level.

[0130] In addition, ciphering with a larger number of key bits becomespossible in error correction, and ciphering is done in a huge black boxsuch as error correction coding or decoding IC or LSI, thus making itdifficult for the general user to decode the ciphering thussignificantly raising data security.

[0131] In addition, data is ciphered using the pre-set key informationand at least a portion of the key information for ciphering is writtenin an area different from the data recording area on the record mediumso that this portion of the key information is read during reproductionand used for deciphering. The key information is not completed withinthe information in the data recording area of the record medium, thusraising the ciphering difficulty.

[0132] In addition, during the scrambling operation mainly aimed atrandomizing the data for removing the same patterns in the data string,at least one of the generating polynominal or the initial value ischanged responsive to the ciphering key such that the pre-existingscrambling may be directly used for ciphering for realizing theciphering by a simplified structure.

[0133] By the above-described data ciphering, prevention of copying orillicit use can be implemented by a simplified configuration, whileapplication to security or to charging system may be realized easily.

[0134] The present invention is not limited to the above-describedembodiments. For example, data conversion may also be by bit addition ora variety of logical operations in addition to by inverters or ExORcircuits as described above. A variety of ciphering techniques, such asdata substitution or transposition responsive to the ciphering keyinformation conversion by shift registers or by various functionprecessing, may also be employed, alone or in combination. Various othermodifications can be made without departing from the purport of theinvention.

1. A data recording method comprising; a sector-forming step of dividinginput digital data in terms of a pre-set data volume as a unit; a headerappending step of appending header to the digital data divided intosectors; an error correction encoding step of appending an errorcorrection code to the digital data having the header appended thereto;a modulating step of modulating the error-corrected encoded digital datain accordance with a pre-set modulation system; an synchronizationappending step of appending a synchronization pattern to the modulateddigital signal; and a recording step of recording the digital signalhaving the synchronization pattern appended thereto on a record medium;wherein an input is ciphered in at least one of the sector forming step,header appending step, error correction encoding step, modulation stepand the synchronization appending step and the resulting ciphered datais outputted.
 2. The data recording method as claimed in claim 1 furthercomprising a scrambling step of randomizing the digital data dividedinto sectors in the sector forming step or the digital data having theheader appended thereto in the header appending step for eliminating thesame pattern; wherein an input is ciphered in at least one of the sectorforming step, header appending step, error correction encoding step,modulation step, synchronization appending step and the scrambling stepand the resulting ciphered data is outputted.
 3. The data recordingmethod as claimed in claim 1 wherein plural sorts of the key informationused in said ciphering are set and switched at a pre-set timing.
 4. Thedata recording method as claimed in claim 1 wherein in which one of thesector forming step, header appending step, error correction encodingstep, modulation step and the synchronization appending step cipheringhas been done is used as the key information.
 5. The data recordingmethod as claimed in claim 1 wherein., of data handled during errorcorrection encoding of the error correction encoding step, at least partconforming to the key information for ciphering is processed with dataconversion.
 6. The data recording method as claimed in claim 1 whereinthe error correction code is the product code.
 7. A data recordingapparatus comprising; sector-forming means for dividing input digitaldata in terms of a pre-set data volume as a unit; header appending meansfor appending header to the digital data outputted by the sector formingmeans; error correction encoding means for appending an error correctioncode to the digital data outputted by the header appending means;modulating means for modulating the digital data outputted by the headerappending means; synchronization appending means for appending asynchronization pattern to the digital signal outputted by themodulation means; and recording means for recording the digital signaloutputted by the modulation means on a record medium; wherein at leastone of the sector forming means, header appending means, errorcorrection encoding means, modulation means and the synchronizationappending means ciphers an input and outputs the resulting ciphereddata.
 8. The data recording apparatus as claimed in claim 7 furthercomprising scrambling means for randomizing the digital data dividedinto sectors by the sector forming means or the digital data having theheader appended thereto by the header appending means for eliminatingthe same pattern; wherein an input is ciphered by at least one of thesector forming means, header appending means, error correction encodingmeans, modulation means, synchronization appending means and thescrambling means and the resulting ciphered data is outputted.
 9. Thedata recording apparatus as claimed in claim 8 further comprising dataconversion means for data-converting at least part of data handled atthe time of error correction encoding and which conforms to the keyinformation for ciphering.
 10. A data record medium having recordedthereon data obtained by forming input digital data into sectors interms of a pre-set data volume as a unit, appending a header to eachsector, and by processing resulting data with header appendage, errorcorrection and encoding, modulation in accordance with a pre-setmodulation system and appendage of a synchronization pattern, theresulting processed data being then ciphered at the time of sectorformation, header appendage, error correction and encoding, modulationor appendage of the synchronization pattern.
 11. A data reproducingmethod comprising: a synchronization separation step for separating asynchronization signal from a digital signal read out from a data recordmedium; a demodulating step of demodulating the digital signal separatedfrom the synchronization signal in accordance with a pre-setdemodulation system; an error correction decoding step of errorcorrecting and decoding the demodulated digital data; a sector resolvingstep of resolving the error corrected and decoded digital data intopre-set sectors; and a header separating step of separating a headerpart of a sector structure of the digital data resolved into sectors;wherein an input has been ciphered in a step for recording associatedwith at least one of the synchronization separation step, demodulatingstep, error correction decoding step, sector resolving step or theheader separating step; and wherein the input is deciphered in a stepfor reproduction associated with the step for recording in whichciphering has been made at the time of recording.
 12. The datareproducing method as claimed in claim 11 further comprising adescrambling step of descrambling digital data scrambled at the time ofrecording, said digital data having been resolved into sectors in thesector resolving step or separated from the header in the headerseparation step; wherein an input has been ciphered in a step forrecording associated with at least one of the synchronization separationstep, demodulating step, error correction decoding step, sectorresolving step, header separating step or the descrambling step; andwherein the input is deciphered in a step for reproduction associatedwith the step for recording in which ciphering has been made at the timeof recording.
 13. A data reproducing method comprising: synchronizationseparation means for separating a synchronization signal from a digitalsignal read out from a data record medium; demodulating means fordemodulating the digital signal outputted by the synchronizationseparation means in accordance with a pre-set demodulation system; errorcorrection decoding means for error correcting and decoding the digitaldata outputted by the demodulating means; sector resolving means forresolving the digital data outputted by the error correction decodingmeans into pre-set sectors; and header separating means for separating aheader part of a sector structure of the digital data outputted by thesector separation means; wherein an input has been ciphered in a stepfor recording associated with at least one of the synchronizationseparation means, demodulating means, error correction decoding means,sector resolving means and the header separating means; and wherein theinput is deciphered by means for reproduction associated with the stepfor recording in which ciphering has been made at the time of recording.14. The data reproducing apparatus as claimed in claim 13 furthercomprising descrambling means for descrambling digital data scrambled atthe time of recording, sad digital data being outputted by said sectorresolving means or said header separation means, wherein an input hasbeen ciphered by means for recording associated with at least one of thesynchronization separation means, modulating means, error correctiondecoding means, sector resolving means, header separating means and thedescrambling means; and wherein the input is deciphered by means forreproduction associated with the means for recording in which cipheringhas been made at the time of recording.
 15. A data recording method forerror correction and encoding input digital data and recording theresulting data on a record medium, wherein at least part of data handledat the time of error correction and encoding and conforming to the keyinformation for ciphering is processed with data conversion.
 16. Thedata recording method as claimed in claim 15 wherein said dataconversion is effected by at least one of the logical processing of thedata and the key information, substitution or transposition employingthe key information, or function precessing.
 17. The data recordingmethod as claimed in claim 15 wherein the number of data processed withsaid data conversion is varied depending on the degree of difficultyencountered in ciphering.
 18. A data recording apparatus for errorcorrection encoding input digital data and recording the resulting dataon a record medium, comprising; input means for inputting the keyinformation for ciphering; and means for data-converting at least partof data handled during the error correction and encoding responsive tothe key information from said input means.
 19. A data record mediumhaving recorded thereon a signal obtained on converting at least part ofdata handled at the time of error correction and encoding of inputdigital data and which conforms to the key information for ciphering.20. A method for reproducing a signal processed with error correctionand encoding and recorded on a record medium, wherein at least part ofdata handled at the time of error correction and encoding and whichconforms to the key information for ciphering is processed with dataconversion, and wherein data handled at the time of error correction anddecoding as a counterpart of the error correction and encoding and whichconforms to the key information for ciphering is processed with databack-conversion as a counterpart of the data conversion.
 21. Anapparatus for reproducing a signal processed with error correction andencoding and recorded on a record medium, comprising: key informationinput means for inputting the key information for ciphering specifyingdata handled at the time of the error correction and encoding and whichhas been processed with data conversion; and error correction anddecoding means for effecting error correction and decoding as acounterpart of the error correction and encoding, said error correctionand decoding means performing error correction and decoding, as acounterpart operation with respect to said data conversion, on data fromthe key information input means conforming to the key information forciphering.
 22. A data recording method in which input data is processedwith signal processing for recording and recorded in a pre-set recordingarea on a record medium, wherein the data is ciphered using the pre-setkey information, and wherein the information recorded in an area otherthan a data recording area on said record medium is used as at least apart of the key information for ciphering.
 23. The data recording methodas claimed in claim 22 wherein at least one of the identificationinformation proper to the record medium, identification informationproper to the recording device, identification information proper to thedevice for producing the record medium, producer/dealer identificationinformation, territory information and the identification informationsupplied from outside is used as the key information.
 24. A datarecording apparatus in which input data is processed with signalprocessing for recording and recorded in a pre-set recording area on arecord medium, wherein the data is ciphered using the pre-set keyinformation, and wherein the information recorded in an area other thana data recording area on said record medium is used as at least a partof the key information for ciphering.
 25. A data record medium on whichdata obtained on ciphering using the key information at least part ofwhich is the information recorded in an area other than a data recordingarea is recorded in said data recording area.
 26. A data reproducingmethod in which signal processing for reproduction is done on digitalsignals read out from a data recording area on a data record medium,said digital signals having been ciphered at the time of recording,wherein deciphering is done using the information recorded in an areaother than a data recording area on said record medium as at least apart of the key information for ciphering.
 27. The data reproducingmethod as claimed in claim 26 wherein at least one of the identificationinformation proper to the record medium, identification informationproper to the recording device, identification information proper to thedevice for producing the record medium, producer/dealer identificationinformation, territory information and the identification informationsupplied from outside is used as the key information.
 28. A datareproducing apparatus in which signal processing for reproduction isdone on digital signals read out from a data recording area on a datarecord medium, said digital signals having been ciphered at the time ofrecording, wherein deciphering is done using the information recorded inan area other than a data recording area on said record medium as atleast a part of the key information for ciphering.
 29. A data recordingmethod comprising; a sector-forming step of dividing input digital datain terms of a pre-set data volume as a unit; a scrambling step forscrambling digital data divided into sectors; a header appending step ofappending header to the scrambled digital data; an error correctionencoding step of appending an error correction code to the digital datahaving the header appended thereto; a modulating step of modulating theerror-corrected encoded digital data in accordance with a pre-setmodulation system; an synchronization appending step of appending asynchronization pattern to the modulated digital signal; and a recordingstep of recording the digital signal .to which has been appended thesynchronization pattern; wherein at least one of the initial value ofthe scrambling step or the generating polynominal is varied responsiveto the key information for ciphering.
 30. A data recording apparatuscomprising; sector-forming means for dividing input digital data interms of a pre-set data volume as a unit; scrambling means forprocessing digital data outputted from said sector forming means withscrambling in which at least one of the pre-set value and the generatingpolynominal is varied responsive t the key information for ciphering;header appending means for appending header to the digital dataoutputted by said scrambling means; error correction encoding means forappending an error correction code to the digital data outputted by thescrambling means; modulating means for modulating the digital dataoutputted by the error correction encoding means in accordance with apreset modulation system; synchronization appending means for appendinga synchronization pattern to the digital signal outputted by themodulation means; and recording means for recording the digital signaloutputted by said synchronization appending means.
 31. A data recordmedium on which there is recorded a signal obtained on forming an inputdigital data into sectors in terms of a pre-set data volume asa unit,the data thus formed into sectors is processed with scrambling in whichat least one of the initial value and the generating polynominal ischanged responsive to the key information for ciphering, a header isappended to the resulting scrambled data, and the resulting data havingthe header is processed with error correction encoding and modulated inaccordance with a pre-set modulation system..
 32. A data reproducingmethod comprising; a synchronization separating step of separating asynchronization signal from a digital signal read out from a data recordmedium; a demodulating step of demodulating the digital signal separatedfrom the synchronization signal in accordance with a pre-set modulationsystem; an error correction decoding step of error correcting anddecoding digital data obtained on demodulation; a sector resolving stepof resolving the error corrected and decoded digital data; a headerseparating step of separating a header portion of a sector structure ofthe digital data resolved into sectors; and a descrambling step ofscrambling the digital data separated from the header by varying atleast one of the initial value or the generating polynominal based onthe key information used for recording.
 33. A data reproducing apparatuscomprising; synchronization separation means for separating asynchronization signal from a digital signal read from a record medium;demodulation means for demodulating the digital signal outputted by thesynchronization separation means in accordance with a pre-set modulationsystem; error correction and decoding means for error correction anddecoding digital data obtained by said demodulation means; sectorresolving means for resolving the digital data outputted by said errorcorrection and decoding means; header separating means for separating aheader portion of a sector structure of the digital data outputted bysaid sector resolving means; and a descrambling step of scrambling thedigital data outputted by said header separating means by varying atleast one of the initial value or the generating polynominal based onthe key information used for recording.